Fin-type field-effect transistors (FinFETs) are increasingly being used to effectively scale integrated circuits. FinFETs, which have a vertical fin structure that function as channels, occupy less horizontal space on the semiconductor substrate and can be formed in logic areas and in memory areas through general semiconductor patterning processes.
However, the continued pressure to further scale integrated circuits has generated a demand for processes for forming smaller and smaller fin structures. The limits of optical resolution in current lithographic processes do not allow for the formation of structures having features small enough for further scaling of integrated circuits. As the demand for feature sizes of these devices continues to get smaller, there is a need to develop new processes for achieving the target sizes.